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ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
FLASH MEMORY
FEATURES
* Thirty-two 64KB erase blocks * Deep Power-Down Mode: 10A MAX * Smart 5 technology: 5V 10% VCC 5V 10% VPP application/production programming 12V VPP tolerant compatibility production programming * Address access time: 90ns * Industry-standard pinouts * Inputs and outputs are fully TTL-compatible * Automated write and erase algorithm * Two-cycle WRITE/ERASE sequence
MT28F016S5
5V Only, Dual Supply (Smart 5)
PIN ASSIGNMENT (Top View) 40-Pin TSOP Type I
OPTIONS
* Timing 90ns access
MARKING
-9
* Package Plastic 40-pin TSOP Type 1 (10mm x 20mm) VG
Part Number Example:
A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC VPP RP# A11 A10 A9 A8 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
MT28F016S5VG-9
GENERAL DESCRIPTION
The MT28F016S5 is a nonvolatile, electrically blockerasable (flash), programmable, read-only memory containing 2,097,152 bytes (8 bits). Writing or erasing the device is done with a 5V VPP voltage, while all operations are performed with a 5V VCC. Due to process technology advances, 5V VPP is optimal for application and production programming. For backward compatibility with SmartVoltage technology, 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 100 cumulative hours. The device is fabricated with Micron's advanced CMOS floatinggate process.
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
The MT28F016S5 is organized into 32 separately erasable blocks. ERASEs may be interrupted to allow other operations with the ERASE SUSPEND command. After the ERASE SUSPEND command is issued, READ operations may be executed. Operations are executed with commands from an industry-standard command set. In addition to status register polling, the MT28F016S5 provides a ready/ busy# (RY/BY#) output to indicate WRITE and ERASE completion. Please refer to Micron's Web site (www.micron.com/ flash/htmls/datasheets.html) for the latest data sheet.
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FUNCTIONAL BLOCK DIAGRAM
Input 8 Buffer
I/O Control Logic 64KB Memory Block (0) 64KB Memory Block (1) 64KB Memory Block (2)
Addr.
A0-A20
Buffer/ Latch
21
10
8
X - Decoder/Block Erase Control
11
Power (Current) Control
Addr. Counter
Input Data Latch
DQ0-DQ7
CE# OE# WE# RP# VCC RY/BY# VPP
Command Execution Logic State Machine YDecoder
64KB Memory Block (29) 64KB Memory Block (30) 64KB Memory Block (31)
8
Y - Select Gates 8 Sense Amplifiers Write/Erase-Bit Compare and Verify
VPP Switch/ Pump
Status Register
Identification Register Output Buffer
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PIN DESCRIPTIONS
TSOP PIN NUMBERS 38 SYMBOL WE# TYPE Input DESCRIPTION Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL) or to the memory array. Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Reset/Power-Down: When LOW, RP# clears the status register, sets the internal state machine (ISM) to the array read mode and places the device in deep power-down mode. All inputs, including CE#, are "Don't Care," and all outputs are High-Z. RP# must be held at VIH during all other modes of operation. Output Enable: Enables data output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Address Inputs: Select a unique, 8-bit byte out of the 2,097,152 available.
9 12
CE# RP#
Input Input
37 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 8, 7, 6, 5, 4, 3, 2, 1, 40 25-28, 32-35 36
OE# A0-A20
Input Input
DQ0-DQ7 RY/BY#
Input/ Output Output
Data I/Os: Data output pins during any READ operation or data input pins during a WRITE. Used to input commands to the CEL. Ready/Busy: Indicates the status of the ISM. When RY/BY# = VOL, the ISM is busy processing a command. If RY/BY# = VOH, the ISM is ready to accept a new command. During deep power-down, device configuration read or erase suspend, RY/BY# = VOH. Output is always active. Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM until completion of the operation, VPP must be at VPPH (5V) (VPP * VCC). VPP = "Don't Care" during all other operations. Power Supply: +5V 10%. Ground. No Connect: This pin may be driven or left unconnected.
11
VPP
Supply
10, 31 29, 30 39
VCC VSS NC
Supply Supply -
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TRUTH TABLE1
FUNCTION Standby Deep Power-Down/Reset READ READ Output Disable WRITE/ERASE 2, 3 ERASE SETUP ERASE CONFIRM 4 WRITE SETUP WRITE 5 READ ARRAY 6 DEVICE CONFIGURATION Manufacturer Compatibility ID Device ID
NOTE: 1. 2. 3. 4. 5. 6.
RP# H L H H H H H H H H H
CE# H X L L L L L L L L L
OE# X X L H H H H H H L L
WE# X X H H L L L L L H H
ADDRESS X X X X X BA X WA X 000000H 000001H
VPP X X X X X VPPH X VPPH X X X
DQ0-DQ7 High-Z High-Z Data-Out High-Z 20H D0H 10H/40H Data-In FFH 89H A0H
RY/BY# VOH VOH VOH VOH VOH VOH AE VOL VOH VOH AE VOL VOH VOH VOH
L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH ("Don't Care"). VPPH = 5V. BA = Block Address; WA = Write Address. Operation must be preceded by ERASE SETUP command. Operation must be preceded by WRITE SETUP command. The READ ARRAY command must be issued before reading the array after writing or erasing.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F016S5 flash memory incorporates a number of features that make it ideally suited for system firmware or data storage. The memory array is segmented into individual erase blocks. Each block may be erased without affecting data stored in other blocks. These memory blocks are read, written and erased by issuing commands to the command execution logic (CEL). The CEL controls the operation of the internal state machine (ISM), which completely controls all WRITE, BLOCK ERASE and VERIFY operations. The ISM protects each memory location from over-erasure and optimizes each memory location for maximum data retention. In addition, the ISM greatly simplifies the control necessary for writing the device in-system or in an external programmer. The Functional Description provides detailed information on the operation of the MT28F016S5 and is organized into these sections: * * * * * * * * * * * * Overview Memory Architecture Output (READ) Operations Input Operations Command Set ISM Status Register Device Configuration Registers Command Execution Error Handling WRITE/ERASE Cycle Endurance Power Usage Power-Up INTERNAL STATE MACHINE (ISM) BLOCK ERASE and WRITE timing are simplified with an ISM that controls all erase and write algorithms in the memory array. The ISM ensures protection against over-erasure and optimizes write margin to each cell. During WRITE operations, the ISM automatically increments and monitors WRITE attempts, verifies write margin on each memory cell and updates the ISM status register. When a BLOCK ERASE is performed, the ISM automatically overwrites the entire addressed block (eliminates overerasure), increments and monitors ERASE attempts, and sets bits in the ISM status register. ISM STATUS REGISTER The ISM status register allows an external processor to monitor the status of the ISM during WRITE and ERASE operations. Two bits of the 8-bit status register are set and cleared entirely by the ISM. These two bits indicate whether the ISM is busy with an ERASE or WRITE task and when an ERASE has been suspended. Additional error information is set in three other bits: VPP status, erase status and write status. These three bits must be cleared by the host system. READY/BUSY# (RY/BY#) OUTPUT In addition to status register polling, the MT28F016S5 provides an asynchronous RY/BY# output to indicate the status of the ISM. RY/BY# is VOH when the state machine is inactive and VOL during a WRITE or ERASE operation. This output is always active. COMMAND EXECUTION LOGIC (CEL) The CEL receives and interprets commands to the device. These commands control the operation of the ISM and the read path (i.e., memory array, device configuration or status register). Commands may be issued to the CEL while the ISM is active. However, there are restrictions on what commands are allowed in this condition. See the Command Execution section for more detail. DEEP POWER-DOWN MODE To allow for maximum power conservation, the MT28F016S5 features a very low current, deep powerdown mode. To enter this mode, the RP# pin is taken to VSS 0.2V. In this mode, the current draw is a maximum of 10A. Entering deep power-down also clears the status register and sets the ISM to the read array mode.
OVERVIEW
SMART 5 TECHNOLOGY Smart 5 technology allows maximum flexibility for in-system READ, WRITE and ERASE operations. For 5Vonly systems, WRITE and ERASE operations may be executed with a VPP voltage of 5V. Due to process technology advances, 5V VPP is optimal for application and production programming. For backward compatibility with SmartVoltage technology, 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 100 cumulative hours. However, no performance increase is realized. For any operation, VCC is at 5V. THIRTY-TWO INDEPENDENTLY ERASABLE MEMORY BLOCKS The MT28F016S5 is organized into 32 independently erasable memory blocks that allow portions of the memory to be erased without affecting the rest of the memory data.
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ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
MEMORY ARCHITECTURE
The MT28F016S5 memory array architecture is designed to allow sectors to be erased without disturbing the rest of the array. The array is divided into 32 addressable blocks that are independently erasable. When blocks rather than the entire array are erased, the total device endurance is enhanced, as is system flexibility. Only the ERASE functions are block-oriented. All READ and WRITE operations are done on a randomaccess basis. Figure 1 illustrates the memory address map. CE# goes HIGH, whichever occurs first. The DQ pins will continue to output new data after each address transition as long as OE# and CE# remain LOW. After power-up or RESET, the device will automatically be in the array read mode. All commands and their operations are covered in the Command Set and Command Execution sections. STATUS REGISTER Performing a READ of the status register requires the same input sequencing as a READ of the array except that the address inputs are "Don't Care." Data from the status register is latched on the falling edge of OE# or CE#, whichever occurs last. If the contents of the status register change during a READ of the status register, either OE# or CE# may be toggled while the other is held LOW to update the output. Following a WRITE or ERASE operation, the device automatically enters the status register read mode. In addition, a READ during a WRITE or ERASE operation will produce the status register contents on DQ0-DQ7. When the device is in ERASE SUSPEND mode, a READ operation will produce the status register contents until another command is issued. While the device is in certain other modes, READ STATUS REGISTER may be given to return to the status register read mode. All commands and their operations are covered in the Command Set and Command Execution sections. DEVICE CONFIGURATION REGISTERS Reading any of the device configuration registers requires the same input sequencing as reading the status register except that specific addresses must be issued. WE# must be HIGH, and OE# and CE# must be LOW. To read the manufacturer compatibility ID, addresses must be at 000000H, and to read the device ID, addresses must be at 000001H. While the device is in certain other modes, READ DEVICE CONFIGURATION may be given to return to the configuration registers read mode. All commands and their operations are covered in the Command Set and Command Execution sections.
OUTPUT (READ) OPERATIONS
The MT28F016S5 features three different types of READs. Depending on the current mode of the device, a READ operation will produce data from the memory array, status register or one of the device configuration registers. In each of these three cases, the WE#, CE# and OE# inputs are controlled in a similar manner. Moving between modes to perform a specific READ will be covered in the Command Execution section. MEMORY ARRAY To read the memory array, WE# must be HIGH, and OE# and CE# must be LOW. Valid data will be output on the DQ pins once these conditions have been met and a valid address is given. Valid data will remain on the DQ pins until the address changes, or until OE# or
0
64KB 64KB 16Mb
31
64KB
Figure 1 Memory Address Map
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INPUT OPERATIONS
The DQ pins are used either to input data to the array or to input a command to the CEL. A command input issues an 8-bit command to the CEL to control the mode of operation of the device. A WRITE is used to input data to the memory array. The following section describes both types of inputs. More information describing how to use the two types of inputs to write or erase the device is provided in the Command Execution section. COMMANDS To perform a command input, OE# must be HIGH, and CE# and WE# must be LOW. Addresses are "Don't Care" but must be held stable, except during an ERASE CONFIRM. The 8-bit command is input on DQ0-DQ7 and is latched on the rising edge of CE# (CE#-controlled) or WE# (WE#-controlled), whichever occurs first. MEMORY ARRAY A WRITE to the memory array sets the desired bits to logic 0s but cannot change a given bit to a logic 1 from a logic 0. Setting any bits to a logic 1 requires that the entire block be erased. To perform a WRITE, OE# must be HIGH, CE# and WE# must be LOW, and VPP must be set to VPPH (5V). A0-A20 provide the address to be written, while the data to be written to the array is input on the DQ pins. The data and addresses are latched on the rising edge of either CE# (CE#-controlled) or WE# (WE#-controlled), whichever occurs first. A WRITE must be preceded by a WRITE SETUP command. Details on how to input data to the array will be covered in the Write Sequence section.
COMMAND SET
To simplify writing of the memory blocks, the MT28F016S5 incorporates an ISM that controls all internal algorithms for the WRITE and ERASE cycles. An 8-bit command set is used to control the device. Details on how to sequence commands are provided in the Command Execution section. Table 1 lists the valid commands.
ISM STATUS REGISTER
The 8-bit ISM status register (see Table 2) is polled to check for WRITE or ERASE completion or any related errors. During or following a WRITE, ERASE or ERASE SUSPEND, a READ operation will output the status register contents on DQ0-DQ7 without prior command. While the status register contents are read, the outputs will not be updated if there is a change in the ISM status unless OE# or CE# is toggled. If the device is not in the write, erase, erase suspend, status register or read mode, READ STATUS REGISTER (70H) can be issued to view the status register contents. All of the defined bits are set by the ISM, but only the ISM and erase suspend status bits are reset by the ISM. The erase, write and VPP status bits must be cleared using CLEAR STATUS REGISTER (50H). This allows the user to choose when to poll and clear the status register. For example, the host system may perform multiple WRITE operations before checking the status register instead of checking after each individual WRITE. Asserting the RP# signal or powering down the device will also clear the status register.
DEVICE CONFIGURATION REGISTERS
The device ID and manufacturer compatibility ID can be read by issuing READ DEVICE CONFIGURATION (90H). To read the desired register, a specific address must be asserted. See Table 3 for more details on the various device configuration registers.
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Table 1 Command Set
COMMAND RESERVED HEX CODE 00H DESCRIPTION This command and all unlisted commands are invalid and should not be called. These commands are reserved to allow for future feature enhancements. Must be issued after any other command cycle before the array can be read. It is not necessary to issue this command after power-up or RESET. Allows the device ID and manufacturer ID to be read. Please refer to Table 3 for more information on the various device configuration registers. Allows the status register to be read. Please refer to Table 2 for more information on the status register bits. Clears status register bits 3-5, which cannot be cleared by the ISM. The first command given in the two-cycle ERASE sequence. The ERASE will not be completed unless followed by ERASE CONFIRM. The second command given in the two-cycle ERASE sequence. Must follow an ERASE SETUP to be valid. Also used during a WRITE/ERASE SUSPEND to resume the WRITE or ERASE. The first command given in the two-cycle WRITE sequence. The write data and address are given in the following cycle to complete the WRITE. Requests a halt of the ERASE and puts the device into the erase suspend mode. When the device is in this mode, only READ STATUS REGISTER, READ ARRAY and ERASE CONFIRM (ERASE RESUME) commands may be executed.
READ ARRAY
FFH
READ DEVICE CONFIGURATION
90H
READ STATUS REGISTER CLEAR STATUS REGISTER ERASE SETUP
70H 50H 20H
ERASE CONFIRM
D0H
WRITE SETUP
40H or 10H B0H
ERASE SUSPEND
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Table 2 Status Register
STATUS BIT # SR7 STATUS REGISTER BIT ISM STATUS 1 = Ready 0 = Busy ERASE SUSPEND STATUS 1 = ERASE suspended 0 = ERASE in progress/completed ERASE STATUS 1 = BLOCK ERASE error 0 = Successful BLOCK ERASE WRITE STATUS 1 = WRITE error 0 = Successful WRITE VPP STATUS 1 = No VPP voltage detected 0 = VPP present DESCRIPTION The ISMS bit displays the active status of the state machine during WRITE or BLOCK ERASE operations. The controlling logic polls this bit to determine when the erase and write status bits are valid. Issuing an ERASE SUSPEND places the ISM in the suspend mode and sets this and the ISMS bit to "1." The ESS bit will remain "1" until an ERASE CONFIRM is issued. ES is set to "1" after the maximum number of ERASE cycles is executed by the ISM without a successful verify. ES is only cleared by a CLEAR STATUS REGISTER command or by a RESET. WS is set to "1" after the maximum number of WRITE cycles is executed by the ISM without a successful verify. WS is only cleared by a CLEAR STATUS REGISTER command or by a RESET. VPPS detects the presence of a VPP voltage. It does not monitor VPP continuously, nor does it indicate a valid VPP voltage. The VPP pin is sampled for 5V after WRITE or ERASE CONFIRM is given. VPPS must be cleared by CLEAR STATUS REGISTER or by a RESET. Reserved for future use.
SR6
SR5
SR4
SR3
SR0-2
RESERVED
Table 3 Device Configuration
DEVICE CONFIGURATION Manufacturer Compatibility ID Device ID ADDRESS 000000H 000001H DATA 89H A0H CONDITION Manufacturer compatibility ID read Device ID read
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COMMAND EXECUTION
Commands are issued to bring the device into different operational modes. Each mode allows specific operations to be performed. Several modes require a sequence of commands to be written before they are reached. The following section describes the properties of each mode, and Table 4 lists all command sequences required to perform the desired operation. READ ARRAY The array read mode is the initial state of the device upon power-up and is also entered after a RESET. If the device is in any other mode, READ ARRAY (FFH) must be given to return to the array read mode. Unlike the WRITE SETUP command (40H), READ ARRAY does not need to be given before each individual read access. DEVICE CONFIGURATION To read the device ID and manufacturer compatibility ID, the READ DEVICE CONFIGURATION (90H) command must be issued. While the device is in this mode, specific addresses must be issued to read the desired information. The manufacturer compatibility ID is read at 000000H, and the device ID is read at 000001H. WRITE SEQUENCE Two consecutive cycles are needed to input data to the array. WRITE SETUP (40H or 10H) is given in the first cycle. The next cycle is the WRITE, during which the write address and data are issued and VPP is brought to VPPH. The ISM will now begin to write the byte. VPP must be held at VPPH until the WRITE is completed (SR7 = 1 and RY/BY# = VOH). While the ISM executes the WRITE, the ISM status bit (SR7) will be at "0" and RY/BY# = VOL, and the device will not respond to any commands. Any READ operation will produce the status register contents on DQ0DQ7. When the ISM status bit (SR7) is set to a logic 1 and RY/BY# = VOH, the WRITE has been completed, and the device will go into the status register read mode until another command is given.
Table 4 Command Sequences
BUS 1ST 2ND CYCLES CYCLE CYCLE REQ'D OPERATION ADDRESS DATA OPERATION ADDRESS DATA 1 2 2 1 2 2 2 2 WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE X X X X X X X X FFH 90H 70H 50H 20H B0H 40H 10H WRITE WRITE WRITE WRITE BA X WA WA D0H D0H WD WD 6, 7 6, 7 5, 6 READ READ CA X CD SRD
COMMANDS READ ARRAY READ DEVICE CONFIGURATION READ STATUS REGISTER CLEAR STATUS REGISTER ERASE SETUP/CONFIRM ERASE SUSPEND/RESUME WRITE SETUP/WRITE ALTERNATE WRITE
NOTE: 1. 2. 3. 4. 5. 6. 7.
NOTES 1 2, 3 4
Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable flash array READ cycles. CA = Configuration Address: 00000H for manufacturer compatibility ID and 00001H for device ID. CD = Configuration Data. SRD = Status Register Data. BA = Block Address. Addresses are "Don't Care" in first cycle but must be held stable. WA = Address to be written; WD = Data to be written to WA.
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ERASE SEQUENCE Executing an ERASE sequence will set all bits within a block to logic 1. The command sequence necessary to execute an ERASE is similar to that of a WRITE. To provide added security against accidental block erasure, two consecutive command cycles are required to initiate an ERASE of a block. In the first cycle, addresses are "Don't Care," and ERASE SETUP (20H) is given. In the second cycle, VPP is brought to VPPH, an address within the block to be erased is issued, and ERASE CONFIRM (D0H) is given. If a command other than ERASE CONFIRM is given, the write and erase status bits (SR4 and SR5) will be set, and the device will be in the read status mode. After the ERASE CONFIRM (D0H) is issued, the ISM will start the ERASE of the addressed block. Any READ operation will output the status register contents on DQ0-DQ7. VPP must be held at VPPH until the ERASE is completed (SR7 = 1 and RY/BY# = VOH). Once the ERASE is completed, the device will be in the status register read mode until another command is issued. ERASE SUSPENSION The only command that may be issued while an ERASE is in progress is ERASE SUSPEND. This command allows other commands to be executed while pausing the ERASE in progress. Once the device has reached the suspend mode, the erase suspend status bit (SR6) and ISM status bit (SR7) will be set and RY/BY# will transition to VOH. The device may now be given a READ ARRAY, ERASE RESUME or READ STATUS REGISTER command. After READ ARRAY has been issued, any location not within the block being erased may be read. If ERASE RESUME is issued before SR6 has been set, the device will immediately proceed with the ERASE in progress. During an ERASE SUSPEND, VPP and RP# must remain at the same levels used for the ERASE. ported for a maximum of 100 cycles and may be connected for up to 100 cumulative hours. Operation outside these limits may reduce the number of WRITE and ERASE cycles that can be performed on the device.
POWER USAGE
The MT28F016S5 offers several power-saving features that may be utilized in the array read mode to conserve power. Deep power-down mode is enabled by bringing RP# to VSS 0.2V. Current draw (ICC) in this mode is a maximum of 10A. When CE# is HIGH, the device will enter standby mode. In this mode, maximum ICC current is 100A. If CE# is brought HIGH during a WRITE or ERASE, the ISM will continue to operate, and the device will consume the respective active power until the WRITE or ERASE is completed.
POWER-UP
The likelihood of unwanted WRITE or ERASE operations is minimized since two consecutive cycles are required to execute either operation. However, to reset the ISM and to provide additional protection while VCC is ramping, one of the following conditions must be met: * RP# must be held LOW until VCC is at valid functional level; or * CE# or WE# may be held HIGH and RP# must be toggled from VCC-GND-VCC. After a power-up or RESET, the status register is reset, and the device will enter the array read mode.
ERROR HANDLING
After the ISM status bit (SR7) has been set, VPP (SR3), write (SR4) and erase (SR5) status bits may be checked. If one or a combination of these four bits has been set, an error has occurred. The ISM cannot reset these four bits. To clear these bits, CLEAR STATUS REGISTER (50H) must be given. Table 6 lists the combination of errors.
,,, ,,,
Note 1 VCC (5V) Address Data NOTE:
RP#
t AA
t RWH
WRITE/ERASE CYCLE ENDURANCE
The MT28F016S5 is designed and fabricated to meet advanced firmware and data storage requirements. To ensure this level of reliability, VPP must be at 5V 10% during WRITE or ERASE cycles. For SmartVoltagecompatible production programming, 12V VPP is sup-
1. VCC must be within the valid operating range before RP# goes HIGH.
Figure 2 Power-Up/Reset Timing Diagram 11
,, ,,
VALID VALID
UNDEFINED
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Table 6 Status Register Error Decode1
STATUS BITS SR5 0 0 0 0 1 1 1 SR4 0 0 1 1 0 0 1 SR3 0 1 0 1 0 1 0 ERROR DESCRIPTION2 No errors VPP voltage error WRITE error WRITE error, VPP voltage not valid ERASE error ERASE error, VPP voltage not valid Command sequencing error
NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER. 2. SR3-SR4 reflect noncumulative results.
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SELF-TIMED WRITE SEQUENCE1 COMPLETE WRITE STATUS-CHECK SEQUENCE
Start (WRITE completed)
Start
WRITE 40H or 10H
SR3 = 0? YES
NO
VPP Error 4, 5
VPP = 5V VPP VCC
SR4 = 0? YES
NO
WRITE Error 5
WRITE Byte Address/Data
WRITE Successful
STATUS REGISTER READ
SR7 = 1? YES Complete Status2 Check (optional)
NO
WRITE Complete 3
NOTE: 1. 2. 3. 4.
Sequence may be repeated for additional WRITEs. Complete status check is not required. Device will be in status register read mode. To return to the array read mode, the FFH command must be issued. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER (50H) should be issued before further WRITE or ERASE operations are attempted. 5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
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SELF-TIMED BLOCK ERASE SEQUENCE1 COMPLETE BLOCK ERASE STATUS-CHECK SEQUENCE
Start (BLOCK ERASE completed)
Start
WRITE 20H
SR3 = 0? YES
NO
VPP Error 5, 6
VPP = 5V VPP VCC
SR4, 5 = 1?
YES
Command Sequence Error 6
WRITE D0H, Block Address
SR5 = 0?
NO
BLOCK ERASE 6
ERASE Busy
STATUS REGISTER or RY/BY# Polling
YES ERASE Successful
NO NO SR7 = 1? YES Complete Status 2 Check (optional) Suspend ERASE? YES Suspend 4 Sequence
ERASE Resumed
ERASE Complete
3
NOTE: 1. 2. 3. 4. 5.
Sequence may be repeated to erase additional blocks. Complete status check is not required. To return to the array read mode, the FFH command must be issued. Refer to the ERASE SUSPEND flowchart for more information. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER (50H) should be issued before further WRITE or ERASE operations are attempted. 6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
14
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
ERASE SUSPEND SEQUENCE
Start (ERASE in progress)
WRITE B0H (ERASE SUSPEND)
VPP = 5V VPP VCC
STATUS REGISTER READ
SR7 = 1? YES
NO
SR6 = 1? YES WRITE FFH (READ ARRAY)
NO
ERASE Completed
Done Reading? YES WRITE D0H (ERASE RESUME)
NO
Resume ERASE
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS ............................. -0.5V to +6V** Input Voltage Relative to VSS ................ -0.5V to +6V** VPP Voltage Relative to VSS ................. -0.5V to +12.6V Temperature Under Bias ...................... -10C to +80C Storage Temperature (plastic) ............ -55C to +125C Power Dissipation ................................................... 1W *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **VCC, input and I/O pins may transition to -2V for <20ns and VCC + 2V for <20ns. Voltage may pulse to -2V for <20ns and 14V for <20ns.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ OPERATING CONDITIONS
(0C TA +70C) PARAMETER/CONDITION 5V Supply Voltage Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs SYMBOL VCC VIH VIL MIN 4.5 2 -0.5 MAX 5.5 VCC + 0.5 0.8 UNITS V V V NOTES 1 1 1
DC OPERATING CHARACTERISTICS
(0C TA +70C) PARAMETER/CONDITION OUTPUT VOLTAGE LEVELS (TTL) Output High Voltage (IOH = -2.5mA) Output Low Voltage (IOL = 5.8mA) OUTPUT VOLTAGE LEVELS (CMOS) Output High Voltage (IOH = -100A) INPUT LEAKAGE CURRENT Any input (0V VIN VCC); All other pins not under test = 0V OUTPUT LEAKAGE CURRENT (DOUT is disabled; 0V VOUT VCC)
NOTE: 1. All voltages referenced to VSS.
SYMBOL VOH1 VOL VOH2
MIN 2.4 - VCC - 0.4
MAX - 0.45 -
UNITS NOTES V 1 V V 1
IL IOZ
-1 -10
1 10
A A
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
CAPACITANCE
(TA = +25C; f = 1 MHz) PARAMETER/CONDITION Input Capacitance Output Capacitance SYMBOL CI CO MAX 8 12 UNITS pF pF NOTES
READ AND STANDBY CURRENT DRAIN
(0C TA +70C; VCC = +5V 10%) PARAMETER/CONDITION READ CURRENT: TTL INPUT LEVELS (CE# = VIL; OE# = VIH; f = 8 MHz; Other inputs = VIL or VIH; RP# = VIH) READ CURRENT: CMOS INPUT LEVELS (CE# 0.2V; OE# * VCC - 0.2V; f = 8 MHz; Other inputs 0.2V or * VCC - 0.2V; RP# = VCC - 0.2V) STANDBY CURRENT: TTL INPUT LEVELS VCC power supply standby current (CE# = RP# = VIH; Other inputs = VIL or VIH) STANDBY CURRENT: CMOS INPUT LEVELS VCC power supply standby current (CE# = RP# = VCC - 0.2V) DEEP POWER-DOWN CURRENT: VCC SUPPLY (RP# = VSS 0.2V) STANDBY OR READ CURRENT: VPP SUPPLY (VPP * VCC) DEEP POWER-DOWN CURRENT: VPP SUPPLY (RP# = VSS 0.2V) SYMBOL ICC1 TYP 8 MAX 50 UNITS NOTES mA 1, 2
ICC2
5
35
mA
1, 2
ICC3
0.2
2
mA
ICC4 ICC5 IPP1 IPP2
65 1 2 2
100 20 15 5
A A A A
NOTE: 1. ICC is dependent on cycle rates. 2. ICC is dependent on output loading. Specified values are obtained with the outputs open.
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
17
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
READ TIMING PARAMETERS ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(0C TA +70C; VCC = +5V 10%)
AC CHARACTERISTICS PARAMETER READ cycle time Access time from CE# Access time from OE# Access time from address RP# HIGH to output valid delay OE# or CE# HIGH to output in High-Z Output hold time from OE#, CE# or address change -9 SYMBOL tRC tACE tAOE tAA tRWH tOD tOH MIN 90 MAX 90 45 90 400 20 0 UNITS NOTES ns ns 1 ns 1 ns ns ns ns
NOTE: 1. OE# may be delayed by tACE minus tAOE after CE# falls before tACE is affected.
AC TEST CONDITIONS
Input pulse levels ............................................... 0.4V to 2.4V Input rise and fall times ................................................ <10ns Input timing reference level .............................. 0.8V and 2V Output timing reference level ........................... 0.8V and 2V Output load ................................. 1 TTL gate and CL = 100pF
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
18
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
A0-A20
,, ,
VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL t RWH VIH
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
READ CYCLE
VALID ADDRESS t RC t AA
CE# t ACE
,, ,,
t OD t OH
OE#
WE#
t AOE
DQ0-DQ7
RP#
VIL
, , ,, ,
VALID DATA
DON'T CARE
UNDEFINED
TIMING PARAMETERS
-9 SYMBOL tRC tACE tAOE
tAA
-9 MAX 90 45 90 UNITS ns ns ns ns SYMBOL tRWH
tOD tOH
MIN 90
MIN
MAX 400 20
UNITS ns ns ns
0
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
19
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
RECOMMENDED DC WRITE/ERASE CONDITIONS
(0C TA +70C; VCC = +5V 10%) PARAMETER/CONDITION VPP WRITE/ERASE lockout voltage VPP voltage during WRITE/ERASE operation VCC WRITE/ERASE lockout voltage SYMBOL VPPLK VPPH VLKO MIN - 4.5 2 MAX 1.5 5.5 - UNITS NOTES V V V 1 2
WRITE/ERASE CURRENT DRAIN
(0C TA +70C; VCC = +5V 10%; VPP = +5V 10% [Note 2]) PARAMETER/CONDITION WRITE CURRENT: VCC SUPPLY WRITE CURRENT: VPP SUPPLY ERASE CURRENT: VCC SUPPLY ERASE CURRENT: VPP SUPPLY ERASE SUSPEND CURRENT: VCC SUPPLY (ERASE suspended) ERASE SUSPEND CURRENT: VPP SUPPLY (ERASE suspended) SYMBOL ICC6 IPP3 ICC7 IPP4 ICC8 IPP5 MAX 35 40 30 20 10 200 UNITS NOTES mA mA mA mA mA A 3 3 3 3 3, 4
NOTE: 1. Absolute WRITE/ERASE protection when VPP VPPLK. 2. For SmartVoltage-compatible production programming, 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 100 cumulative hours. 3. Sampled, not tested, 100%. 4. Parameter is specified when device is not accessed. Actual current draw will be ICC8 (5V VCC) plus current of operation being executed while the device is in suspend mode.
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
20
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS: WE# (CE#)-CONTROLLED WRITES
(0C TA +70C; VCC = +5V 10%)
AC CHARACTERISTICS PARAMETER WRITE cycle time WE# (CE#) HIGH pulse width WE# (CE#) pulse width Address setup time to WE# (CE#) HIGH Address hold time from WE# (CE#) HIGH Data setup time to WE# (CE#) HIGH Data hold time from WE# (CE#) HIGH CE# (WE#) setup time to WE# (CE#) LOW CE# (WE#) hold time from WE# (CE#) HIGH VPP setup time to WE# (CE#) HIGH RP# HIGH to WE# (CE#) LOW delay WRITE duration BLOCK ERASE duration WRITE recovery to READ VPP hold time from status data valid, RY/BY# HIGH WE# (CE#) HIGH to RY/BY# LOW WE# (CE#) HIGH to busy status (SR7 = 0) SYMBOL tWC tWPH (tCPH) tWP (tCP) tAS tAH tDS tDH tCS (tWS) tCH (tWH) tVPS tRS tWED1 tWED2 tWR tVPH tRYBY tWB -9 MIN 90 25 50 40 5 40 5 0 0 100 1,000 6 600 0 0 90 200 UNITS ns ns ns ns ns ns ns ns ns ns ns s ms ns ns ns ns NOTES
WRITE AND ERASE DURATION CHARACTERISTICS
5V VPP PARAMETER WRITE time BLOCK ERASE time BLOCK WRITE time ERASE SUSPEND latency to READ
NOTE: 1. Typical values measured at TA = +25C. 2. Assumes no system overhead. 3. Typical WRITE times use checkerboard data pattern.
TYP 8 0.5 0.5 9
MAX TBD TBD TBD 12
UNITS NOTES s s s s 1 1 1, 2, 3 1
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
21
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
WRITE/ERASE CYCLE WE#-CONTROLLED WRITE/ERASE
VIH A0-A20 VIL VIH CE# VIL tCS VIH OE# VIL VIH WE# VIL tDS DQ0-DQ7 VIH VIL VOH RY/BY# VOL VHH VIH RP# VIL VPPH2 VPP VPPH1 VIL WRITE SETUP or ERASE SETUP input WRITE or block address asserted, and WRITE data or ERASE CONFIRM WRITE or ERASE executed, status register checked for completion Command for next operation issued tVPS [12V VPP] [5V VPP] tVPH tRS tRYBY CMD in tDH tDS CMD/ Data-in tWB tDH Status (SR7=0) Status (SR7=1) CMD in tWP tCH tWC tWPH tWED1, 2 tWR Note 1 tAS tAH tAS AIN tAH
DON'T CARE
TIMING PARAMETERS
-9 MIN 90 25 50 40 5 40 5 0 0 -9 MIN 100 1,000 0 90 200 6 600 0
SYMBOL
tWC tWPH tWP tAS tAH tDS tDH tCS tCH
UNITS ns ns ns ns ns ns ns ns ns
SYMBOL
tVPS2 tRS tVPH2 tRYBY tWB tWED1 tWED2 tWR
UNITS ns ns ns ns ns s ms ns
NOTE: 1. Address inputs are "Don't Care" but must be held stable. 2. Measured with VPP = VPPH = 5V.
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
22
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
WRITE/ERASE CYCLE CE#-CONTROLLED WRITE/ERASE
VIH A0-A20 VIL VIH WE# VIL VIH OE# VIL VIH CE# VIL tDS DQ0-DQ7 VIH VIL VOH RY/BY# VOL VHH VIH RP# VIL VPPH2 VPP VPPH1 VIL WRITE SETUP or ERASE SETUP input WRITE or block address asserted, and WRITE data or ERASE CONFIRM WRITE or ERASE executed, status register checked for completion Command for next operation issued tVPS [12V VPP] [5V VPP] tVPH tRS tRYBY CMD in tDH tDS CMD/ Data-in tWB tDH Status (SR7=0) Status (SR7=1) CMD in tCP tWS tWH tWC tCPH tWED1, 2 tWR Note 1 tAS tAH tAS AIN tAH
DON'T CARE
TIMING PARAMETERS
-9 MIN 90 25 50 40 5 40 5 0 0 SYMBOL
tVPS2 tRS tVPH2 tRYBY tWB tWED1 tWED2 tWR
SYMBOL
tWC tCPH tCP tAS tAH tDS tDH tWS tWH
UNITS ns ns ns ns ns ns ns ns ns
-9 MIN 100 1,000 0 90 90 6 600 0
UNITS ns ns ns ns ns s ms ns
NOTE:
1. Address inputs are "Don't Care" but must be held stable. 2. Measured with VPP = VPPH = 5V.
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
23
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
40-PIN PLASTIC TSOP I (10mm x 20mm)
.795 (20.19) .780 (19.81) .0197 (0.50) TYP 1 .727 (18.47) .721 (18.31) 40 .010 (0.25)
PIN #1 INDEX .397 (10.08) .010 (0.25) .006 (0.15) .391 (9.93)
20
21 .010 (0.25)
.007 (0.18) .005 (0.13) SEE DETAIL A .047 (1.20) MAX
.004 (0.10) GAGE PLANE .008 (0.20) .002 (0.05)
.024 (0.60) .016 (0.40) DETAIL A .0315 (0.80)
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc.
2 Meg x 8 Smart 5 Even-Sectored Flash Memory F42.p65 - Rev. 1/00
24
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.

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